Release Note for Stanford Bootcode Firmware ============================================ 5755, 5755m ---------------------------- Version 3.12 ---- 1/24/06 ---------------------------- 1. Enabled ASIC fix for tx Ethernet packet corruption on late collision Enhancement: CQ#22908, CQ#14561, CQ#14521 Since the ASIC is fixed and verified by ASIC team, we are enabling the fix in this version. 2. Removed all register 0x7d00 access Problem: CQ#22832 Accessing register 0x7d00 can cause the corruption of content when reference clock was not stable in some system. Cause: When the device was put into D3 power state, due to the clock issue, the PCIE registers become not accessible. If an access to register may cause the content corruption. Fix: Removed all 0x7d00 register access. Impact: Since the hardware will automatically shutdown PCIE transmitter and receiver in D3 state; therefore, there is no power consumption change in normal OS shutdown/hibernate. When the system was powered down in D0 state, such as ungraceful/DOS shutdown, we will see more power consumption. From the lab measurement, we observed the current draw increased from 172mA to 236mA. 3. Changed revision reading Problem: CPU reads incorrect silicon revision id in D3 power state. Cause: In D3 power state, except OOB, the PCI/PCIE registers are not accessible. All reads returns zero. Because of this, the read is not reliable. Fix: Instead of reading from register 0x68, the code is changed to read the revision id from register 0x2018. The register 0x2018 is available at all time. ---------------------------- Version 3.11 ---- 12/22/05 ---------------------------- 1. Enabled Slow Clock for Cable Sense mode Enhancement: Enabled slow clock mode for cable sense so when cable is unplug, we can conserve more power. ---------------------------- Version 3.10 ---- 12/09/05 ---------------------------- 1. Force PCIE link polarity Problem: CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254 In some platform, the PCIE link polarity comes up incorrectly. Cause: ASIC could not handle all cases correctly. Fix: Wait until PCIE link comes up. Then based on the link polarity status detected by ASIC polarity auto detect, firmware will then force the PCIE link to the correct polarity. 2. Enable refclock auto switching Problem: The workaround in version 3.07, #1 is not stable. CPU could read "good" link indication without REFCLK. Cause: Without clock, the interface can timeout and return anything left in the data bus. Fix: Enable auto clock switching. When enabled, the clock will automatically switched to internal clock when there is no ref. clock available. 3. Enable clock request for A1 or new revision Enhancement: The clock request was disabled in version 3.06, #3 for A0 issue. Starting this version, the clock request will be enabled back for A1 or newer devices. ---------------------------- Version 3.09 ---- 11/14/05 ---------------------------- 1. CQ14315 Problem: CQ14315 If L0s is enabled on the BRCM chip a "yellow bang", or a system hang condition can occur. Cause: During the L0s to L0 exit transition, symbol lock can be lost if the system reference clock has not fully stabilized what leads the PCI-E link training state machine to go through the "detect" state. Going through "detect" causes an internal reset to the BRCM chip what causes "yellow bang" and/or a system hang condition based on the chipset configuration. Fix: 1. Change Serdes RX Timer from 768 ns to 2 uS to make sure the Serdes CDR is stable before it sends data to the Physical Layer. 2. Increase FTS Count from 1uS to 2.25 uS to avoid intermittent GRC Reset when L0s is enabled. Since RX Timer value and FTS Count change only needed before PCIE link training, bootcode will initialize those values and retrain the PCIE link during cold reset only. When driver reset, this workaround is bypassed to avoid PCIE link retrain. Impact: Increasing the amount of FTS required to transition from L0s to L0, will impact the overall, top performance. 2. Enable Frequency Multiplier only for the Mobile Device Enhancement: ASIC team has verified this enhancement in ASIC; therefore, this version enables the ASIC enhancement for Frequency Multiplier. Impact: This feature is only available for M-part. 3. Fixed WoL was not working issue. Problem: CQ#14614 WoL was not working on OOB case. Cause: Version 3.07 (#1) added workaround for platforms that show an unstable PCIE refclk during power up. Nevertheless, there is a limitation to this workaround as to where it requires VMAIN to be present. In systems where there is no VMAIN present and there is no PCI-E REFCLK at all for the cases outlined above the bootcode will loop forever, therefore not enabling WoL. Fix: Added a condition to the "unstable PCI-E Refclk" workaround to apply this fix only when there is VMain present. In cases where there is no VMAIN present, the boot code will no longer check/wait for a "stable PCI-E Refclk" before continuing. 4. Fixed Link Histogram Issue. Problem: In DVT testing, Link histogram results seemed to be worsen in bootcode version 3.08. Cause: The change in version 3.08, item#2, removes all Gphy workaround. The workaround included hybrid bias change, adc bias change, and pll startup bandwidth change. The hardware fix still have incorrect PLL startup bandwidth value. By removing the workaround, the sympton has showed up. Fix: Added the adjustment for the PLL startup bandwidth. ---------------------------- Version 3.08 ---- 10/18/05 ---------------------------- 1. Fixed Cable Sense mode Problem: The Cable Sense mode was initialized incorrectly Cause: Initialized to wrong register. Fix: Fixed the error 2. Not to apply poor BER performance workaround Problem: The workaround for poor BER (Bit Error Rate) with cable length 70m or less was causing the problem. Cause: For 5755/5755m, the BER problem has been fixed in ASIC already. If the workaround was applied, by changing hybrid bias current, would yield the unwanted current. Fix: Removed the workaround 3. Move GPIO initialization to Phase1 code Enhancement: Originally, activating VAUX power was done in phase 2 bootcode. However, once driver waited for phase1 signature, driver may start to configure GPIO for WoL setting. The 2nd phase GPIO initialization may destroy driver's setting. This problem was worked around by driver by waiting for phase2 bootcode to be loaded before the GPIO initialization. This change does not affect anything since driver already have the work around. ---------------------------- Version 3.07 ---- 9/30/05 ---------------------------- 1. Worked around unstable PCIE refclk issue Problem: Device does not come up on some machine platform. (bootcode v3.05) Cause: In some particular system, the PCIE refclk was not stable for a long period of time. Accessing PCI config. space registers, 0x7d00 and 0x7e00 block registers relying on this clock. When the clock is not available, all access to those registers will timeout and read will return zero. The read-modify-write instruction performed at 0x7d00, reads zero (due to unavailable clock and stall for a long time), then clock become available (due to long timeout delay) and write modified zero value back to register. As result, destroyed the register content. With value zero in 0x7d00 shuts down PCIE bus and hence the device become invisible from the bus. The fix in bootcode version 3.06, changing read-modify-write to absolute write is not good because basically that write does not go through. (Due to unavailable refclk) In this case, it worked because the hardware default value was good enough to bring up the device. Since all access performed to 0x7d00, 0x7e00, and PCI config. space is invalid until the clock is available, many initialization may not be done correctly; or at least it may reads incorrect revision ID. Therefore, to ensure the code is executed properly, we need to ensure the clock is there first before proceeding with initialization. Fix: Put a wait loop until refclk is stable before move on to initialization process. 2. Enable L1 support advertizement for M part Enhancement: This version enables Link Capability L1 support for M part. ---------------------------- Version 3.06 ---- 9/29/05 ---------------------------- 1. Fixed PCIE Serdes shutdown routine Problem: CQ#14165 There still a time bootcode will write 0 to PCIE Serdes control register. Cause: There is a time the register is not readable. Using read-modify-write method may cause reading wrong value and write clear all necessary control bits. Fix: Changed to absolute write after reset to initialize PCIE Serdes control register. 2. Load ASF with Driver reset Enhancement: This is the 2nd phase of rev. A0 workaround. Allowing ASF code to be loaded with driver reset. 3. Disable ClockReq Problem: The chip will get a GRC_RESET when going from D3Hot to D0 state Cause: When ClockReq is enabled, the chip will get a GRC_RESET when going from D3Hot to D0 state. The hardware default for mobile part is enabled. Fix: Disable ClockReq for mobile part. Note: The ClockReq is automatically disabled by h/w on a non-M parts; therefore, this change does not affect non-M parts. ---------------------------- Version 3.05 ---- 9/22/05 ---------------------------- 1. Fixed PCIE Serdes shutdown routine Problem: When the bootcode was trying to shutdown device, bootcode has disabled PCIE transmitter and receiver; however, other bits in the same register was destroyed. Cause: Absolute write routine was used. Fix: Changed to read-modify-write. ---------------------------- Version 3.04 ---- 9/21/05 ---------------------------- 1. Enabled GPIO Problem: By hardware default, GPIO function was disabled. Because of this, all GPIO function was not working. This was result in NIC mode WoL function not to work or system hang for some machine. Cause: Stanford requires firmware to enable GPIO in order to use it. Fix: Enabled GPIO function ---------------------------- Version 3.03 ---- 9/20/05 ---------------------------- 1. Fixed the version 3.02 workaround Problem: After posting negate of drv/firmware handshake signature, there is still a small window of time that register read could be corrupted. Cause: The second phase of bootcode still accessing NVRAM. (To check/load Management firmware) Fix: Moved the signature posting right before entering the service loop. In case of management firmware is enabled, no negate of signature is posted. (It will be the management firmware's responsibility to post the signature) ---------------------------- Version 3.02 ---- 9/16/05 ---------------------------- 1. Applied ASIC bug workaround The following is only applied to A0 revision a. Post negate of drv/firmwaqw handshake signature at the end of 2nd phase bootcode loading. b. Disabled VPD read/write for driver reset. (It returns garbage if read) c. Disabled ROM service for driver reset. d. Disabled ASF/IPMI/UMP firmware for driver reset. e. Added firmware suspension function. f. A value 0 is read after NVRAM access. ---------------------------- Version 3.01 ---- 9/14/05 ---------------------------- 1. Removed Nvram config1 initialization Problem: There is address lockout error Cause: Per design, Nvram config1 register (0x7014) modification is not allowed when address lockout feature is enabled. The original firmware was overriding this register to adjust the NVRAM clock access speed. When write to config1 register is attempt, address lockout error 9 was posted (at reg. 0x7000 [31:28]) Fix: Removed the config1 register initialization. ---------------------------- Version 3.00 ---- 9/13/05 ---------------------------- 1. Initial official release Problem: 2nd phase bootcode did not run. Cause: The stack pointer was initialized to 0x20000. For Stanford, the mbuf memory size only has 48k, 0x10000-0x1c000; therefore, the stack pointer should be initialized to 0x1c000 instead of 0x20000. Fixed: Fixed the stack pointer ---------------------------- Version 2.07 ---- 6/2/05 ---------------------------- 1. Changed NVRAM pin straps Problem: Stanford pin strap is not compatible with Baxter. The pin strap mapping needed to be changed. Fix: Changed the bin strap to Stanford. Note: Due to b57diag, the version has been skipped from 2.01 to 2.07. (B57diag treat version 2.07 smaller number as an old version doesn't support directory structure.) ---------------------------- Version 2.01 ---- 6/2/05 ---------------------------- 1. Firmware does not program revision register 0x8. 2. The indirect access address registers, 0x78/0x7c will not be cleared by firmware. 3. Set bit 23 of 0x7c04 after programming MAC address 0x410/0x414 to prevent future change of register 0x164/0x168. 4. The link capability, register 0xdc is not touched. ---------------------------- Version 2.00 ---- 4/1/05 ---------------------------- 1. Initial engineering release This branch of built of Baxter v3.10.