Release Note for Jade/Caesar Bootcode Firmware ============================================== 5787, 5787f, 5787m, 5754, 5754m ---------------------------- Version 3.11 ---- 1/24/06 ---------------------------- 1. Changed CQ#22832 fix Problem: CQ#22832 The CQ#22832 request to change 0x7d00 access to read-modify-write still have problem on some system when reference clock is not stable. Cause: Absolute-write may corrupt register 0x7D00 content under corner conditions. Fix: Changed to code to not to touch 0x7d00 at all. Impact: There is no impact if the WOL feature is not enabled in our device. There is also no impact if the system always broadcasts PME_Turn_Off tlp message to downstream before it removed the main power in system OOB or hibernate scenario. There is little power consumption increase when a) WOL is enabled in our device and b) the system ungracefully removes the main power without sending out PME_Turn_Off tlp message to downstream in system OOB or hibernate scenario. The current draw in our device is measured at 236mA as compared to 172mA before this change. 2. Enabled ASIC fix for tx Ethernet packet corruption on late collision Enhancement: CQ#22908, CQ#14561, CQ#14521 Since the ASIC is fixed and verified by ASIC team, we are enabling the fix in this version. ---------------------------- Version 3.10 ---- 1/18/06 ---------------------------- 1. Disabled clkreq# Enhancement: CQ#22829 Disable clkreq# for all the revision of the Mobile parts until the feature is fully verified with engineering system. This is done by clearing bit 18 of 0xdc and bit 8 of 0xe0. 2. Changed 0x7d00 access to absolute write Problem: CQ#22832 A value of 0xa000 was left in register 0x7d00 and caused the device to disappear. Cause: When the device was put into D3 power state, due to the clock issue, the PCIE registers become not accessible. If read-modify-write were used at this point, the read will fail and returning zero to CPU. Then, after CPU modify the content and write back, many critical bits are cleared in register 0x7d00. As result, the subsequence reset, the device could not establish PCIE link and disappears from the host. Fix: Changed 0x7d00 register to absolute write instead of read-modify-write. 3. Changed revision reading Problem: CPU reads incorrect silicon revision id in D3 power state. Cause: In D3 power state, except OOB, the PCI/PCIE registers are not accessible. All reads returns zero. Because of this, the read is not reliable. Fix: Instead of reading from register 0x68, the code is changed to read the revision id from register 0x2018. The register 0x2018 is available at all time. 4. Enabled ASIC fix for CQ#11011 Enhancement: The decision has been made to enable this ASIC fix to be consistent with Shasta/Baxter. This is done by clearing bit 18 of 0x7d00. ---------------------------- Version 3.09 ---- 1/09/06 ---------------------------- 1. Changed 2.5V voltage regulator value Enhancement: The DVT tests with Jade A1 parts indicate that the 2.5V regulator default output is low. Bootcode now will change the 2.5V regulator so it is close to 2.5V. 2. Enable clock request for A2 or newer revision Enhancement: Due to the ASIC bug, the clock request was disabled in version 3.03, #2. Since this feature has been fixed in A2 or newer revision, starting this version, the clock request will be enabled back for A2 or newer devices. ---------------------------- Version 3.08 ---- 12/08/05 ---------------------------- 1. Fixed device disappearing issue Problem: CQ#22330 When VMain is turned off, either from OOB case or turn off the system by power button, next boot, the device disappears to the host. Cause: The workaround logic put in v3.07, #1 to force PCIE link polarity requires to wait until the link is up when there is VMain. However, the PCIE Tx/Rx was turned off when bootcode sense there was no VMain to save power. On next boot, since the code to turn back on PCIE Tx/Rx was placed after the PCIE link polarity workaround to wait for PCIE link, the link never came up and stuck in the loop forever. Fix: Moved the code to turn on PCIE Tx/Rx prior to PCIE link polarity workaround. ---------------------------- Version 3.07 ---- 12/06/05 ---------------------------- 1. Force PCIE polarity Problem: CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254 In some platform, the PCIE link polarity comes up incorrectly. Cause: ASIC could not handle all cases correctly. Fix: Wait until PCIE link comes up. Then based on the link polarity status detected by ASIC polarity auto detect, firmware will then force the PCIE link to the correct polarity. 2. Enable refclock auto switching Problem: The workaround in version 3.06, #1 is not stable. CPU could read "good" link indication without REFCLK. Cause: Without clock, the interface can timeout and return anything left in the data bus. Fix: Enable auto clock switching. When enabled, the clock will automatically switched to internal clock when there is no ref. clock available. 3. Removed ref.clock advertisement in A0/A1. Problem: When ref.clock support is advertised, the device gets unwanted reset. Cause: If clkreq# enabled, it may intermittently caused SerDes PLL state machine misbehavior and lead to GRC reset. Fix: This problem will be fixed in ASIC A2. For A0/A1, firmware will disable ref.clock advertisement. ---------------------------- Version 3.06 ---- 11/22/05 ---------------------------- 1. Fixed WoL was not working issue. Problem: CQ#14614 WoL was not working on OOB case. Cause: Version 3.03 (#1) added workaround for platforms that show an unstable PCIE refclk during power up. Nevertheless, there is a limitation to this workaround as to where it requires VMAIN to be present. In systems where there is no VMAIN present and there is no PCI-E REFCLK at all for the cases outlined above the bootcode will loop forever, therefore not enabling WoL. Fix: Added a condition to the "unstable PCI-E Refclk" workaround to apply this fix only when there is VMain present. In cases where there is no VMAIN present, the boot code will no longer check/wait for a "stable PCI-E Refclk" before continuing. 2. Fixed Link Histogram Issue. Problem: In DVT testing, Link histogram results seemed to be worsen in bootcode version 3.05. Cause: The change in version 3.05, item#2, removes all Gphy workaround. The workaround included hybrid bias change, adc bias change, and pll startup bandwidth change. The hardware fix still have incorrect PLL startup bandwidth value. By removing the workaround, the sympton has showed up. Fix: Added the adjustment for the PLL startup bandwidth. ---------------------------- Version 3.05 ---- 10/18/05 ---------------------------- 1. Fixed Cable Sense mode Problem: The Cable Sense mode was not enabled correctly. Cause: There was a confusion between SuperAirplane mode and Cable Sense mode. SuperAirplane mode with GPHY configuration should be equivalent to Cable Sense mode. The previous, version 3.04, was setting SuperAirplane mode without configuring GPHY. Therefore, it would not function as Cable Sense mode. Fix: Instead of using SuperAirplane mode (bit 25), now the code will use Cable Sense mode (bit 26) so it does not need to program GPHY. 2. Not to apply poor BER performance work around Problem: The work around for poor BER (Bit Error Rate) with cable length 70m or less was causing the problem. Cause: For 5754/5787 family, the BER problem has been fixed in ASIC already. If the work around was applied, by changing hybrid bias current, would yield the unwanted current. Fix: Removed the work around ---------------------------- Version 3.04 ---- 10/12/05 ---------------------------- 1. Fixed Cable Sense mode Problem: The Cable Sense mode could not be enabled. Cause: The bit to check for mobile part was wrong. Fix: Changed to correct way of detecting mobile part. 2. Move GPIO initialization to Phase1 code Problem: CQ#14105 Unexpected POR was seen at Windows S3/S4 shutdown when using 64k EEPROM. Cause: Originally, activating VAUX power was done in phase 2 bootcode. However, once driver waited for phase1 signature, driver may start to configure GPIO for WoL setting. The 2nd phase GPIO initialization may destroy driver's setting. This problem was worked around by driver by waiting for phase2 bootcode to be loaded before the GPIO initialization. However, when the NVRAM device is 64K EEPROM, phase 2 takes over 500ms to be loaded. To meet the Windows Fast Initiative requirement, driver could only wait for 200ms. When driver times out, it will proceed with GPIO initialization and later, destroyed by 2nd phase bootcode. This caused power glitch and generated POR. Fix: Moved the GPIO initialization to phase 1. ---------------------------- Version 3.03 ---- 10/3/05 ---------------------------- 1. Worked around unstable PCIE refclk issue Problem: Device does not come up on some machine platform. (bootcode v3.02) Cause: In some particular system, the PCIE refclk was not stable for a long period of time. Accessing PCI config. space registers, 0x7d00 and 0x7e00 block registers relying on this clock. When the clock is not available, all access to those registers will timeout and read will return zero. The read-modify-write instruction performed at 0x7d00, reads zero (due to unavailable clock and stall for a long time), then clock become available (due to long timeout delay) and write modified zero value back to register. As result, destroyed the register content. With value zero in 0x7d00 shuts down PCIE bus and hence the device become invisible from the bus. Since all access performed to 0x7d00, 0x7e00, and PCI config. space is invalid until the clock is available, many initialization may not be done correctly; or at least it may read incorrect revision ID. Therefore, to ensure the code is executed properly, we need to ensure the clock is there first before proceeding with initialization. Fix: Put a wait loop until refclk is stable before move on to initialization process. 2. Disable ClockReq Problem: The chip will get a GRC_RESET when going from D3Hot to D0 state Cause: When ClockReq is enabled, the chip will get a GRC_RESET when going from D3Hot to D0 state. The hardware default for mobile part is enabled. Fix: Disable ClockReq for mobile part. Note: The ClockReq is automatically disabled by h/w on a non-M parts; therefore, this change does not affect non-M parts. ---------------------------- Version 3.02 ---- 9/22/05 ---------------------------- 1. Fixed PCIE Serdes shutdown routine Problem: When the bootcode was trying to shutdown device, bootcode has disabled PCIE transmitter and receiver; however, other bits in the same register was destroyed. Cause: Absolute write routine was used. Fix: Changed to read-modify-write. 2. Removed Nvram config1 initialization Problem: There is address lockout error Cause: Per design, Nvram config1 register (0x7014) modification is not allowed when address lockout feature is enabled. The original firmware was overriding this register to adjust the NVRAM clock access speed. When write to config1 register is attempt, address lockout error 9 was posted (at reg. 0x7000 [31:28]) Fix: Removed the config1 register initialization. ----------------------------- Version 3.01 ---- 9/7/05 ---------------------------- 1. Enabled PCIE transmitter & receiver upon reset Problem: When WoL is enabled in NIC mode, device disappears after turning off power. Cause: When bootcode detects no VMain, it turns off PCIE transmitter & receiver. Those two bits are only reset upon power on reset (POR) but not other resets. Therefore, when power it on with power switch, the device getting PE reset does not bring PCIE link out of disabled state. As result, the device become not visible. Fix: Enable PCIE transmitter and reciever upon reset. Note: When using version 3.00, this problem occured, the only to recover is to short jumper J405 and then use Alt-Ctl-Del to restart the computer. ---------------------------- Version 3.00 ---- 9/6/05 ---------------------------- 1. Initial official release Problem: Version 2.00, 2nd phase bootcode did not run. Cause: The stack pointer was initialized to 0x20000. For Jade, the mbuf memory size only has 48k, 0x10000-0x1c000; therefore, the stack pointer should be initialized to 0x1c000 instead of 0x20000. Fixed: Fixed the stack pointer ---------------------------- Version 2.00 ---- 6/2/05 ---------------------------- 1. Initial engineering release This is a branch of Stanford v2.01. GPIOs will not be changed to output pins for the one not in use.